Embodiments herein generally relate to forming oxide-filled trenches in a process that advantageously applies the tendency for the well-known oxidation processes to consume silicon, so as to convert all the silicon substrate material between multiple trenches into an oxide. Therefore, because all of the silicon between the trenches is consumed by the oxidizing process, the multiple smaller trenches are combined into a single larger trench filled with the oxide.
One conventional disclosure U.S. patent application 2005/0012158, incorporated herein by reference, presents a process where trenches are filled by growing oxide within the trenches. Another (U.S. patent application 2004/0121532 incorporated herein by reference) discloses a method of forming a trench by selectively etching the oxide-inhibiting layer to form a LOCOS opening. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Other well-known processes for filling trenches with insulators or oxides include chemical vapor deposition (CVD), plasma CVD, spin-on oxide, etc. For example, U.S. patent application No. 2003/0143817, incorporated herein by reference, discloses filling multiple trenches with insulator or oxide material.
However, conventional processes for forming trenches filled with insulators often create a void or keyhole within the center of the insulator material. Further, such conventional processes may leave oxide on top of the wafer which must be removed. For example, as shown in FIGS. 1 and 2, voids 10 often remain within the oxide or insulator material 12. As shown in FIG. 2, these voids 10 can often be filled with conductors 20 such as polysilicon that are utilized in subsequent processing steps. The conventional solutions to compensate for (or avoid) forming such voids are complex, and time- and material-intensive.
For example, one solution to the problem of forming voids is disclosed in U.S. Patent Application No. 2003/0143852, incorporated herein by reference, which proposes a complex process of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. This method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.
The above process demonstrates the complexity and time- and material-intensive nature of such conventional “solutions”. Further, the conventional methodologies of forming oxide layers can produce a non-planar surface which requires subsequent chemical mechanical polishing (CMP) or other similar planarization processes. Therefore, there is a need for a process that easily and quickly creates oxide-filled trenches without forming voids therein and that does not require subsequent planarization processes.